Dual circuit signal control



De- 2 1958 H. T. cHAPEK v:a1-Al.. 2,862,663

DUAL CIRCUIT SIGNAL CONTROL Filed Deo. 16. 1955 United States Patent z,s62 ,66s

DUAL CIRCUIT SIGNAL CONTROL Henry T. AChapek and Heard S. Lowry, Jr., Manchester,- Tenn., assignors to the United States of America as represented by the Secretary of the Air Force Application December 16, 1955, Serial No. 553,670

4 Claims. (Cl. 235-92) This invention relates tocomputing, and particularly to computing circuitry utilizing successions of computing elements, each including signal read-out and indicating facilities.

A feature of the invention is the provision of novel resetting facilities permitting interruption of the normal trend of signal transfer (e. g. digital computing) at any stage of a ycomplete cycle, by means operatingto modify the potential characteristics of the signal transfer elements themselves. The said resetting facilities herein disclosed and claimed are in the nature of improvements upon and extensions of resetting arrangements disclosed and claimed in our copending application No. 550,508 tiled December l, 1955. V

The invention is illustrated as incorporated in signal transferelernents of the Eccles-Jordan Atype trigger amplifier. The action of this two-tube circuit depends upon the fact that current flows through only one tube at a time. This form of multivibrator employs direct coupling between the anodes and grids of the two tubes. It is a circuit v possessing two conditions of stable equilibrium. One condition is when tube 1 is conducting and tube 2 is cut-off; f

their. functions and remain in the new condition as long as no plate current ows in the cut-off tube. Because of this sudden reversal or ilip-flopping from one state of equilibrium to the other, this type of circuit is referred to as a flip-flop circuit.

The flip-dop circuits are arranged serially to form a counting or analogous signal transfer system. Means are provided so that the same tube in each of the flip-flop circuits always condu-cts in the null position. One method is to drive the desired tube to the conducting state in preparation for counting. The counting circuit then receives information in the form of repeated pulses, the number of repetitions imparting the desired information. These pulses actuate some or all of the Hip-flop circuits which are arranged serially. It would be desirable to have some visual indication of the state of each of the ipflop circuits in the counting system and simultaneously a completely'independent output to any external device.

After a train of pulses into the counter, the visual indications for each of the flip-flop circuits will then show whether or not they are in a null condition. If not, means are provided to reset the flip-flop circuits to the null condition in preparation for another counting cycle.

An object of this invention is to provide improved means for resetting the flip-llop circuits simultaneously effective upon all units of the computing chain.

Still further objects and advantages of this invention will be apparent in the following description and 4claims considered with the accompanying drawing showing a schematic wiring diagram embodying the invention.

Referring to the drawing, Fig. l, there are shown successive computing elements connected serially. Each one 2,862,663 Patented Dec. 2, 1958 of the elements is identical and each element is a modi-v iied type Eccles-Jordan flip-flop circuit. This flip-flop circuit is comprised of two triode vacuum tubes 2 and 3. Each of the triodes 2 and 3 is adapted to receive an actuating input pulse from common input terminal 39. This input pulse is impressed upon the grid 4 of tube 2 through capacitor 6 and upon the grid 5 of tube 3 through capacitor 7. Each tube'is provided with a grid resistor to ground, 8 for tube 2 and 9 for tube 3. Resistor 18 in shunt with capacitor 20 couples the anode 10 of tube 2 to grid 5 of tube 3. Resistor 19 in shunt with capacitor 21 couples the anode of tube 3 to grid 4 of tube 2. The anode of tube 2 is loaded by a series connected resistor which is divided into resistors 22 and 26. The output of the Hip-flop circuit 1 is taken from point 28 between resistors 22 and 26. This output is adapted to feed the next succeeding lijp-flop circuit. Anode 11 of tube 3 is loaded by series connected resistor 23 and inductance 25. Inductance 25, an energizing coil of relay 40, is shunted by diode 27. Single pole-double throw switch 29 is actuated by inductance 25. There are two voltage sources 34 at volts and 33 at -|25 volts. Connected in series between 33 and 34 are resistors 31, 32 and one side 36 of switch 29. In shunt with resistor 32 and voltage sour-ce 33 is neon tube 30. The other side 37 of switch 29 is the output line 38 to output connection 35.

The elements above-described correspond substantially to the elements similarly identified in our aforesaid copending application. The resetting means of the present invention, on the other hand, incorporates structure and a mode of operation differing from the resetting means of our aforesaid copending application in the following respects: Cathode 12 of tube 2 and theV corresponding cathodes of the other triode tubes in the successive computing elements are tied together by common conductor 56; cathode 13 of tube 3 and the corresponding cathodes of the other triode tubes in the successive computing elements are tied together by common conductor 57; a common ycathode circuit comprising resistors 14, 15 and b`y-pass capacitor 16 is provided for all of the said computing elements; resistor 15 is normally shunted by switch 17; switch 17 is actuated by energizing coil 58 of relay 41; the'actuating pulse is provided by source 5S; common conductor 56 provides one set of cathodes with cathode resistor 14toA ground; common conductor 57 provides the other set of cathodes with a common divided resistor comprising resistors 14 and 15; cathode resistor 14 is common to both sets of cathodes.

With the flip-flop circuit in the null position (i. e. at rest) tube 2 is conducting and tube 3 is nonconducting. Relay 40 is not energized so that single throw-double pole switch 29 connects resistor 31 which is in series with resistor 32 to point 36 and then across voltage sources 33 and 34, thus forming a voltage dividing network. Neon tube 30 is in shunt with only a part of this voltage dividing network and receives an inadequate voltage to ionize it. With tube 2 conducting and tube 3 nonconducting, one method of actuating the flip-flop circuit is to apply a negative pulse to the common input 39. This will decrease the grid potential of tube 2. The plate potential of tube 2 rises sharply, carrying with it the grid potential of tube 3, thus allowing tube 3 to conduct. The accompanying decrease in plate potential of tube 3 forces the grid potential of tube 2 below cut-off. Tube 3 remains in a conducting state and tube 2 remains in a nonconducting state.

When tube 3 is in a conducting state and tube 2 is nonconducting, relay 40 is energized by reason of the current flow through inductance 25. Diode 27 damps the transients through inductance 25. The series resistor 23 isolates the capacity to ground of inductance 25, thus preventing this capacity to ground from aiecting the action of the dip-flop. Resistor 23 also allows compensation for dierent values of relay inductance.

The inductance 2S being in an energized state single pole-double throw switch 29 is actuated and'fvoltage source 34 is shifted from contact 36 to 37. Neon tube 3G is now connected in series with resistor 31 and both' are across voltage sources 33 and 34. There is adequate voltage .to ionlze neo-n tube 30 which glows. This serves as a visual indication of the state of the flip-flop. Simultaneously, line 38 providesa contact output directly to terminal 35. 'I'his may also serve as a convenient means for reading out the state of the counter without disturbing the count.

At any stage of a lcounting cycle or at its completion, it may be desirable or necessary to reset the iiip-iiop in the computing chain to a null .or rest condition, thereby requiring all of tubes 2 'to revert to a conducting condition and tubes 3 to a nonconducting one. A resetting pulse is provided from source 55. This will energize coil 58 of relay 41. Switch 17, which normally closes the contacts of relay 41 and thereby shunting resistor 15, is opened. This will provide all the cathodes tied to cathode 13 of tube 3 with a common divided resistance, namely, resistors 14 and 15. Where the tubes 3 of successive computing elements are in a conductingstate, lthe bias on the tubes 3 will increase in a negative direction. The plate potentials of the tubes 3 will rise, carrying with it the grid potential of the tubes 2 thus allowing the tubes 2 to conduct. The accompanying decrease in plate potentials of the tubes 2 will force the grid potentials of the tubes 3 below cut-off. Tubes 2 remain in a conducting state and tubes 3 in a nonconducting state. The resetting pulse having actuated relay 41 is now discontinued and coil 5S of relay 41 loses its energization. Switch 17 again'shunts resistor 15. The ip-ops of the computing chain are now in a stand-by condition available for another counting cycle.

What is claimed is:

l. A computing system comprising a succession of twostate devices having individual anode circuits, individual excitation grid circuits, and a common cathode circuit, means for transferring signals from each of said twostate devices to the next succeeding two-state device, relayoperated switch means in said common cathode circuit, and means for sending a resetting pulse through said relay means to modify the potential characteristics of said signal transfer means.

2. A computing system comprising a succession of dual circuit two-state devices, means whereby the outputs'of said two-state devices are available directly, means for visual indication of the state of each of the said twostate devices, means for progressively transferring the signal output from each of said two-state devices along said succession of devices, circuit-.loading potential control means common to all of said two-state devices, means for modifyingthe action`of said `potential control means to effect a simultaneous resetting of all of said two-state devices to a predetermined one of said two-states, said rersetting means including a relay and means for sending a resetting .pulse through said, relay to modify potential characteristics of allv of said signal output transfer means, said modifying means being comprised of switch means in a common cathode circuit for all of said two-state devices, and means for causing said switch means to control the operation of said common cathode circuit.

3. A computing system as defined in claim 2, including resistance in'shunt with-said switch means, said resistance means being normally short-circuited by said switch means.

4. A computing system comprising a succession of twostate devices having individual anode circuits, individual anode circuits, individual excitation grid circuits and a common cathode circuit, means for transferring signals from each of said two-state devices to the next succeeding two-state device, means in said common cathode circuit for simultaneously resetting said two-state devices to a predetermined one of said two states, said common cathode circuit including a plurality of conductors of said two-state devices, cathode potential-controlling means uniformly atfectingall of said vconductors, relay means in shunt relationshipto said'potential-controlling means, and cooperatingetherewithto produce'a predetermined potential difference in said common cathode -circuit in response to each energzation-of-said relay means.

References Cited -in-the file of this patent UNITED STATES PATENTS 2,168,198 Frink Aug. 1, 1939 2,521,787 Grosdof Sept. 12, 1950 2,521,788 Grosdoff Sept. 12, 1950 2,765,426 Faulkner Oct. 2, 1956 2,792,525 McArdley May 14, 1957 

